`timescale 1ns/1ps
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// *********************************************************************************
// Project Name : 
// Author       : Dark
// Create Time  : 2023-01-17 20:13:47
// Revise Time	: 2023-01-17 20:13:47
// File Name    : regfile.sv
// Abstract     :

module regfile (
	input	logic			clk,    // Clock
	input	logic			rst_n,  // Synchronous reset active low
	
	input	logic	[4:0]	rs1_addr,   //rs1
	input	logic	[4:0]	rs2_addr,	//rs2
	input	logic	[4:0]	wb_addr,	//rd
	input	logic	[31:0]	wb_data,
	input	logic			wb_en,

	output	logic	[31:0]	rs1_data,
	output	logic	[31:0]	rs2_data
	
);


//=================================================================================
// Parameter declaration
//=================================================================================



//=================================================================================
// Signal declaration
//=================================================================================

	reg [31:0]regbank [0:31];  //32I

//=================================================================================
// Body
//=================================================================================
	// Write Back Registers
	genvar i;
	generate
		for(i=0;i<32;i++)
			always_ff @(posedge clk) 
				if(~rst_n) 
					regbank[i] <= 32'd0;
			 	else if (wb_en&&(wb_addr == i))
			 		regbank[i] <= wb_data;
	endgenerate
	// Read from rs1

/*addi x1,x0,1
addi x2,x0,2
addi x3,x0,3
addi x4,x1,3
wb = rs , same  time*/
	always @(*) begin 
		if (rs1_addr==5'd0)
			rs1_data = 32'b0; //x0 hardwired to logical 0
		else if (wb_addr == rs1_addr && wb_en && wb_addr!=5'd0)
			rs1_data = wb_data;
		else
			rs1_data = regbank[rs1_addr];
	end
	// Read from rs2
	always @(*) begin  
		if (rs2_addr==5'd0)
			rs2_data = 32'b0; //x0 hardwired to logical 0
		else if (wb_addr == rs2_addr && wb_en && wb_addr!=5'd0)
			rs2_data = wb_data;
		else
			rs2_data = regbank[rs2_addr];
	end
// use for one cycle cpu
//	assign rs1_data  = (rs1_addr==5'd0)?32'd0:regbank[rs1_addr];//x0 hardwired to logical 0
//	assign rs2_data  = (rs2_addr==5'd0)?32'd0:regbank[rs2_addr];

 	
endmodule : regfile

